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19-5237; rev 0; 4/10 ordering information general description the max11202 is an ultra-low-power (< 300 f a max active current), high-resolution, serial output adc. this device provides the highest resolution per unit power in the industry and is optimized for applications that require very high dynamic range with low power such as sensors on a 4ma to 20ma industrial control loop. the max11202 provides a high-accuracy internal oscillator that requires no external components. when used with the specified data rates, the internal digital filter provides more than 80db rejection of 50hz or 60hz line noise. the max11202 provides a simple 2-wire serial interface in the space-saving, 10-pin f max m package. the max11202 operates over the -40 n c to +85 n c tem - perature range. applications sensor measurement (temperature and pressure) portable instrumentation battery applications weigh scales features s 24-bit full-scale resolution 20.5-bit noise-free resolution at 13.75sps 19-bit noise-free resolution at 120sps s 720nv rms noise (max11202b) s 3ppm inl s no missing codes s ultra-low power dissipation operating mode current drain < 300a (max) sleep mode current drain < 0.1a s 2.7v to 3.6v analog supply voltage range s 1.7v to 3.6v digital and i/o supply voltage range s fully differential signal inputs s fully differential reference inputs s internal system clock 2.4576mhz (max11202a) 2.2528mhz (max11202b) s external clock s serial 2-wire interface (clock input and data output) s on-demand offset and gain self-calibration s -40c to +85c operating temperature range s 2kv esd protection s lead(pb)-free and rohs-compliant max package note: all devices are specified over the -40 n c to +85 n c oper - ating temperature range. + denotes a lead(pb)-free/rohs-compliant package. max is a registered trademark of maxim integrated products, inc. selector guide part pin-package output rate (sps) MAX11202AEUB+ 10 f max 120 max11202beub+ 10 f max 13.75 resolution (bits) 4-wire spi, 16-pin qsop, programmable gain 4-wire spi, 16-pin qsop 2-wire serial, 10-pin max 24 max11210 max11200 max11201 (with buffers) max11202 (without buffers) 20 max11206 max11207 max11208 18 max11209 max11211 max11212 16 max11213 max11203 max11205 24-bit, single-channel, ultra-low-power, delta sigma adc with 2-wire serial interface max11202 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
2 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. any pin to gnd .................................................... -0.3v to +3.9v avdd to gnd ....................................................... -0.3v to +3.9v dvdd to gnd ...................................................... -0.3v to +3.9v analog inputs (ainp, ainn, refp, refn) to gnd .............................................. -0.3v to (v avdd + 0.3v) digital inputs and digital outputs to gnd .............................................. -0.3v to (v dvdd + 0.3v) esd hb (avdd, ainp, ainn, refp, refn, dvdd, clk, sclk, rdy /dout, gnd) ............................................ q 2kv (note 1) continuous power dissipation (t a = +70 n c) 10-pin f max (derate 5.6mw/ n c above +70 n c) .......... 444mw operating temperature range .......................... -40 n c to +85 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -55 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics (v avdd = +3.6v, v dvdd = +1.8v, v refp - v refn = v avdd ; internal clock, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c under normal conditions, unless otherwise noted.) absolute maximum ratings note 1: human body model to specification mil-std-883 method 3015.7. parameter symbol conditions min typ max units adc performance noise-free resolution (notes 2, 3) nfr max11202a 19 bits max11202b 20.5 noise (notes 2, 3) v n max11202a 2.1 f v rms max11202b 0.72 integral nonlinearity inl (note 4) -10 +10 ppmfsr zero error v off after calibration, v refp - v refn = 2.5v -13 1 +13 ppmfsr zero drift 50 nv/ n c full-scale error after calibration, v refp - v refn = 2.5v (note 5) -30 3 +30 ppmfsr full-scale error drift 0.05 ppmfsr/ n c power-supply rejection avdd dc rejection 70 80 db dvdd dc rejection 90 100 analog inputs/reference inputs common-mode rejection cmr dc rejection 90 123 db 50hz/60hz rejection, max11202a 90 50hz/60hz rejection, max11202b 144 normal-mode 50hz rejection nmr 50 max11202b (note 6) 65 80.5 db normal-mode 60hz rejection nmr 60 max11202b (note 6) 73 87 db common-mode voltage range gnd v avdd v absolute input voltage low input voltage gnd - 30mv v high input voltage v avdd + 30mv dc input leakage sleep mode (note 2) q 1 f a ain dynamic input current 5 f a ref dynamic input current 7.5 f a maxim integrated 24-bit, single-channel, ultra-low-power, delta sigma adc with 2-wire serial interface max11202
3 electrical characteristics (continued) (v avdd = +3.6v, v dvdd = +1.8v, v refp - v refn = v avdd ; internal clock, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c under normal conditions, unless otherwise noted.) parameter symbol conditions min typ max units ain input capacitance 10 pf ref input capacitance 15 pf ain voltage range ainp - ainn -v ref +v ref v ref voltage range v avdd v input sampling rate f s max11202a 246 khz max11202b 225 ref sampling rate max11202a 246 khz max11202b 225 logic inputs (sclk, clk) input current input leakage current q 1 f a input low voltage v il 0.3 x v dvdd v input high voltage v ih 0.7 x v dvdd v input hysteresis v hys 200 mv external clock max11202a 2.4576 mhz max11202b 2.2528 logic output ( rdy /dout) output low level v ol i ol = 1ma; also tested for v dvdd = 3.6v 0.4 v output high level v oh i oh = 1ma; also tested for v dvdd = 3.6v 0.9 x v dvdd v floating state leakage current output leakage current q 10 f a floating state output capacitance 9 pf power requirements analog supply voltage avdd 2.7 3.6 v digital supply voltage dvdd 1.7 3.6 v total operating current avdd + dvdd 230 300 f a dvdd operating current 45 60 f a avdd operating current 185 245 f a avdd sleep current 0.4 2 f a dvdd sleep current 0.35 2 f a 2-wire serial-interface timing characteristics sclk frequency f sclk 5 mhz sclk pulse width low t 1 60/40 duty cycle, 5mhz clock 80 ns sclk pulse width high t 2 40/60 duty cycle, 5mhz clock 80 ns sclk rising edge to data valid transition time t 3 40 ns maxim integrated 24-bit, single-channel, ultra-low-power, delta sigma adc with 2-wire serial interface max11202
4 electrical characteristics (continued) (v avdd = +3.6v, v dvdd = +1.8v, v refp - v refn = v avdd ; internal clock, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c under normal conditions, unless otherwise noted.) note 2: these specifications are not fully tested and are guaranteed by design and/or characterization. note 3: v ainp = v ainn . note 4: ppmfsr is parts per million of full-scale range. note 5: positive full-scale error includes zero-scale errors. note 6: the max11202a has no normal-mode rejection at 50hz or 60hz. parameter symbol conditions min typ max units sclk rising edge data hold time t 4 allows for positive edge data read 3 ns rdy /dout fall to sclk rising edge t 5 0 ns next data update time; no read allowed t 6 max11202a 155 f s max11202b 169 data conversion time t 7 max11202a 8.6 ms max11202b 73 data ready time after calibration starts (cal + cnv) t 8 max11202a 208.3 ms max11202b 256.1 sclk high after rdy /dout goes low to activate sleep mode t 9 max11202a 0 8.6 ms max11202b 0 73 time from rdy /dout low to sclk high for sleep-mode activation t 10 max11202a 0 8.6 ms max11202b 0 73 data ready time after wake-up from sleep mode t 11 max11202a 8.6 ms max11202b 73 data ready time after calibration from sleep mode wake-up (cal + cnv) t 12 max11202a 208.4 ms max11202b 256.2 maxim integrated 24-bit, single-channel, ultra-low-power, delta sigma adc with 2-wire serial interface max11202
5 typical operating characteristics (v avdd = 3.6v, v dvdd = 1.8v, v refp - v refn = avdd; internal clock; t a = t min to t max , unless otherwise specified. typical values are at t a = +25 n c.) analog active current vs. avdd voltage (max11202a) max11202 toc01 avdd voltage (v) current (a) 3.45 3.30 3.15 3.00 2.85 120 140 160 180 200 220 240 v dvdd = 1.8v t a = +85 c t a = +25 c t a = -45 c 100 2.70 3.60 analog active current vs. avdd voltage (max11202b) max11202 toc02 avdd voltage (v) current (a) 3.45 3.30 3.15 3.00 2.85 120 140 160 180 200 220 240 v dvdd = 1.8v t a = +85 c t a = +25 c t a = -45 c 100 2.70 3.60 analog sleep current vs. avdd voltage (max11202a/ max11202b) max11202 toc03 avdd voltage (v) current (a) 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 0.2 0.4 0.6 0.8 1.0 0 2.7 3.6 v dvdd = 1.8v t a = -45c t a = +85c t a = +25c active supply current vs. temperature (max11202a) max11202 toc04 temperature (c) current (a) 75 55 35 15 -5 -25 50 100 150 200 250 300 0 -45 95 total v avdd = 3.6v v dvdd = 1.8v active supply current vs. temperature (max11202b) max11202 toc05 temperature (c) current (a) 75 55 35 15 -5 -25 50 100 150 200 250 300 0 -45 95 total v avdd = 3.6v v dvdd = 1.8v sleep current vs. temperature (max11202a/ max11202b) max11202 toc06 temperature (c) current (a) 75 55 35 15 -5 -25 0.2 0.4 0.6 0.8 1.0 0 -45 95 v avdd = 3.6v v dvdd = 1.8v v avdd v dvdd total digital active current vs. dvdd voltage max11202 toc07 dvdd voltage (v) current (a) 3.4 3.2 2.8 3.0 2.0 2.2 2.4 2.6 1.8 50 60 70 80 90 100 110 120 130 40 1.6 3.6 v avdd = 3.6v t a = +85c, +25c, -45c max11202a max11202b digital sleep current vs. dvdd voltage (max11202a/ max11202b) max11202 toc08 dvdd voltage (v) current (a) 3.3 3.1 2.9 2.7 2.5 2.3 2.1 1.9 0.5 1.0 1.5 2.0 2.5 3.0 0 1.7 3.5 v avdd = 3.6v t a = -45c t a = +25c t a = +85c internal oscillator frequency vs. temperature max11202 toc09 temperature (c) frequency (mhz) 75 55 35 15 -5 -25 2.1 2.2 2.3 2.4 2.5 2.6 2.0 -45 95 v dvdd = 1.8v v avdd = 3.0v max11202a max11202b maxim integrated 24-bit, single-channel, ultra-low-power, delta sigma adc with 2-wire serial interface max11202
6 typical operating characteristics (continued) (v avdd = 3.6v, v dvdd = 1.8v, v refp - v refn = avdd; internal clock; t a = t min to t max , unless otherwise specified. typical values are at t a = +25 n c.) internal oscillator frequency vs. avdd voltage max11202 toc10 avdd voltage (v) frequency (mhz) 3.45 3.30 3.15 3.00 2.85 2.2 2.3 2.4 2.5 2.6 2.1 2.70 3.60 v dvdd = 1.8v max11202a max11202b noise vs. input voltage max11202 toc11 input voltage (v) noise (v rms ) 2.0 1.5 -2.0 -1.5 -1.0 0 0.5 -0.5 1.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 -2.5 2.5 v ref = 2.5v max11202a max11202b noise vs. temperature max11202 toc12 temperature (c) noise (v rms ) 75 55 -25 -5 15 35 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 -45 95 v ref = 3.0v max11202a max11202b noise histogram (max11202a, 120sps) max11202 toc13 adc output (v) number of readings (%) 9.0 6.7 4.3 2.0 -0.3 2 4 6 8 10 12 14 0 -2.7 11.3 30,000 consecutive readings t a = +25c v ref = 2.5v rms = 2.1v mean = 5.0v adc output (v) number of readings (%) 6.29 5.44 3.74 4.59 2.89 2.04 1.19 noise histogram (max11202b, 13.75sps) 2 4 6 8 10 12 14 16 18 20 0 max11202 toc14 30,000 consecutive readings t a = +25c v ref = 2.5v rms = 0.72v mean = 4.1v long-term adc readings (max11202a) max11202 toc15 time (min) adc reading (v) 0.8 0.6 0.4 0.2 -10 -5 0 5 10 15 -15 0 1.0 t a = +25c v in = 0v rms = 2.1v long-term adc readings (max11202b) max11202 toc16 time (min) adc reading (v) 8 6 4 2 -4 -3 -2 -1 0 1 2 3 4 5 -5 01 0 t a = +25c v in = 0v rms = 0.72v offset error vs. v ref (max11202a/ max11202b) max11202 toc17 v ref voltage (v) offset error (ppmfsr) 3.5 3.0 2.5 2.0 1.5 -0.5 0 0.5 1.0 1.5 2.0 -1.0 1.0 4.0 v ref = v refp - v refn t a = +85c t a = -45c t a = +25c offset error vs. temperature (max11202a/ max11202b) max11202 toc18 temperature (c) offset error (ppmfsr) 75 55 35 15 -5 -25 0.5 1.0 1.5 2.0 2.5 0 -45 95 calibrated at +25c maxim integrated 24-bit, single-channel, ultra-low-power, delta sigma adc with 2-wire serial interface max11202
7 typical operating characteristics (continued) (v avdd = 3.6v, v dvdd = 1.8v, v refp - v refn = avdd; internal clock; t a = t min to t max , unless otherwise specified. typical values are at t a = +25 n c.) integral nonlinearity vs. input voltage (max11202a/ max11202b) max11202 toc19 input voltage (v) inl (ppmfsr) 2.0 1.5 0.5 1.0 -1.5 -1.0 -0.5 0 -2.0 -8 -6 -4 -2 0 2 4 6 8 10 -10 -2.5 2.5 v avdd = 3.0v v dvdd = 1.8v v ref = 2.5v v in(cm) = 1.5v t a = +25c t a = -45c t a = +85c max11202 toc20 temperature (c) normalized full-scale error (ppmfsr) full-scale error vs. temperature (max11202a/ max11202b) 75 55 15 35 -5 -25 -8 -6 -4 -2 0 2 4 6 8 10 -10 -45 v ref = 2.5v +fs error -fs error psrr vs. frequency (max11202a) max11202 toc21 frequency (hz) psrr (db) 10k 1k 100 10 -120 -100 -80 -60 -40 -20 0 -140 1 100k v dvdd v avdd cmrr vs. frequency (max11202a/ max11202b) max11202 toc23 frequency (hz) cmrr (db) 10k 1k 100 10 -120 -100 -80 -60 -40 -20 0 -140 1 100k max11202a max11202b psrr vs. frequency (max11202b) max11202 toc22 frequency (hz) psrr (db) 10k 1k 100 10 -120 -100 -80 -60 -40 -20 0 -140 1 100k v dvdd v avdd normal-mode frequency response (max11202a) max11202 toc24 frequency (hz) gain (db) 100 10 -120 -100 -80 -60 -40 -20 0 -140 11 k normal-mode frequency response (max11202b) max11202 toc25 frequency (hz) gain (db) 100 10 -120 -100 -80 -60 -40 -20 0 -140 11 k normal mode rejection of 50hz to 60hz (max11202b) max11202 toc26 frequency (hz) gain (db) 65 60 55 50 45 -120 -100 -80 -60 -40 -20 0 -140 40 70 maxim integrated 24-bit, single-channel, ultra-low-power, delta sigma adc with 2-wire serial interface max11202
8 pin description functional diagram pin configuration timing clock generator digital logic and serial- interface controller digital filter (sinc 4 ) 3rd-order delta-sigma modulator clk avdd max11202 refp refn ainp ainn dvdd gnd sclk rdy/dout pin name function 1 gnd ground. ground reference for analog and digital circuitry. 2 refp differential reference positive input. refp must be more positive than refn. connect refp to a voltage between avdd and gnd. 3 refn differential reference negative input. refn must be more negative than refp. connect refn to a voltage between avdd and gnd. 4 ainn negative fully differential analog input 5 ainp positive fully differential analog input 6 avdd analog supply voltage. connect a supply voltage between +2.7v to +3.6v with respect to gnd. 7 dvdd digital supply voltage. connect a digital supply voltage between +1.7v to +3.6v with respect to gnd. + 1 2 3 4 5 10 9 8 7 6 clk sclk dvdd ainn refn refp gnd max11202 max top view avdd ainp rdy/dout maxim integrated 24-bit, single-channel, ultra-low-power, delta sigma adc with 2-wire serial interface max11202
9 detailed description the max11202 is an ultra-low-power (< 240 f a active), high-resolution, low-speed, serial-output adc. this device provides the highest resolution per unit power in the industry and is optimized for applications that require very high dynamic range with low power such as sensors on a 4ma to 20ma industrial control loop. the max11202 pro - vides a high-accuracy internal oscillator, which requires no external components. when used with the specified data rates, the internal digital filter provides more than 80db rejection of 50hz or 60hz line noise. the max11202 provides a simple, system-friendly, 2-wire serial interface in the space-saving, 10-pin f max package. power-on reset (por) the max11202 utilizes power-on reset (por) supply- monitoring circuitry on both the digital supply (dvdd) and the analog supply (avdd). the por circuitry ensures proper device default conditions after either a digital or analog power-sequencing event. the max11202 performs a self-calibration operation as part of the startup initialization sequence whenever a digital por is triggered. it is important to have a stable reference voltage available at the refp and refn pins to ensure an accurate calibration cycle. if the reference voltage is not stable during a por event, the part should be calibrated once the reference has stabilized. the part can be programmed for calibration by using 26 sclks as shown in figure 3. the digital por trigger threshold is approximately 1.2v and has 100mv of hysteresis. the analog por trigger threshold is approximately 1.25v and has 100mv of hys - teresis. both por circuits have lowpass filters that pre - vent high-frequency supply glitches from triggering the por. the analog supply (avdd) and the digital supply (dvdd) pins should be bypassed using 0.1f capaci - tors placed as close as possible to the package pin. analog inputs the max11202 accepts two analog inputs (ainp and ainn). the modulator input range is bipolar (-v ref to +v ref ). internal oscillator the max11202 incorporates a highly stable internal oscillator that provides the system clock. the system clock runs the internal state machine and is trimmed to 2.4576mhz (max11202a) or 2.2528mhz (max11202b). the internal oscillator clock is divided down to run the digital and analog timing. reference the max11202 provides differential inputs refp and refn for an external reference voltage. connect the external reference directly across the refp and refn to obtain the differential reference voltage. the common- mode voltage range for v refp and v refn is between 0 and v avdd . the differential voltage range for refp and refn is 1v to v avdd . digital filter the max11202 contains an on-chip, digital lowpass filter that processes the 1-bit data stream from the modulator using a sinc 4 (sinx/x) 4 response. when the device is operating in single-cycle conversion mode, the filter is reset at the end of the conversion cycle. when operat - ing in continuous conversion latent mode, the filter is not reset. the sinc 4 filter has a -3db frequency equal to 24% of the data rate. serial-digital interface the max11202 communicates through a 2-wire inter - face, with a clock input and data output. the output rate is predetermined based on the package option (max11202a at 120sps and max11202b at 13.75sps). pin description (continued) 8 rdy /dout data ready output/serial data output. this output serves a dual function. in addition to the serial data output function, the rdy /dout also indicates that the data is ready when the rdy is logic low. rdy /dout changes on the rising edge of sclk. 9 sclk serial clock input. apply an external serial clock to sclk. 10 clk external clock signal input. the internal clock shuts down when clk is driven by an external clock. use a 2.4576mhz oscillator (max11202a) or a 2.2528mhz oscillator (max11202b). maxim integrated 24-bit, single-channel, ultra-low-power, delta sigma adc with 2-wire serial interface max11202
10 2-wire interface the max11202 is compatible with the 2-wire interface and uses sclk and rdy /dout for serial communica - tions. in this mode, all controls are implemented by tim - ing the high or low phase of the sclk. the 2-wire serial interface only allows for data to be read out through the rdy /dout output. supply the serial clock to sclk to shift the conversion data out. the rdy /dout is used to signal data ready, as well as reading the data out when sclk pulses are applied. rdy /dout is high by default. the max11202 pulls rdy / dout low when data is available at the end of conver - sion, and stays low until clock pulses are applied at the sclk input. on applying the clock pulses at sclk, the rdy /dout outputs the conversion data on every sclk positive edge. to monitor data availability, pull rdy / dout high after reading the 24 bits of data by supplying a 25th sclk pulse. the different operational modes using this 2-wire inter - face are described in the following sections. data read following every conversion the max11202 indicates conversion data availability, as well as the retrieval of data through the rdy /dout out - put. the rdy /dout output idles at the value of the last bit read unless a 25th sclk pulse is provided, causing rdy /dout to idle high. the timing diagram for the data read is shown in figure 1. once a low is detected on rdy /dout, clock pulses at sclk clock out the data. data is shifted out msb first and is in binary twos complement format. once all the data has been shifted out, a 25th sclk is required to pull the rdy /dout output back to the idle high state. see figure 2. if the data is not read before the next conversion data is updated, the old data is lost, as the new data overwrites the old value. data read followed by self-calibration to initiate self-calibration at the end of a data read, pro - vide a 26th sclk clock pulse. after reading the 24 bits of conversion data, a 25th positive edge on sclk pulls the rdy /dout output back high, indicating the end of the data read. provide a 26th sclk clock pulse to initi - ate a self-calibration routine starting on the falling edge of the sclk. a subsequent falling edge of rdy /dout indicates data availability at the end of calibration. the timing is illustrated in figure 3. data read followed by sleep mode the max11202 can be put into sleep mode to save power between conversions. to activate the sleep mode, idle the sclk high any time after the rdy /dout output goes low (that is, after conversion data is available). it is not required to read out all 24 bits before putting the part in sleep mode. sleep mode is activated after the sclk is held high (see figure 4). the rdy /dout output is pulled high once the device enters sleep mode. to come out of the sleep mode, pull sclk low. after the sleep mode is deactivated (when the device wakes up), conversion starts again and rdy /dout goes low, indicating the next conversion data is available (see figure 4). single-conversion mode for operating the max11202 in single-conversion mode, activate and deactivate sleep mode between conver - sions as described in the data read followed by sleep mode section). single-conversion mode reduces power consumption by shutting down the device when idle between conversions. see figure 4. single-conversion mode with self-calibration at wake-up the max11202 can be put in self-calibration mode imme - diately after wake-up from sleep mode. self-calibration at wake-up helps to compensate for temperature or supply changes if the device is shut down for extensive periods. to automatically start self-calibration at the end of sleep mode, all the data bits must be shifted out followed by the 25th sclk edge to pull rdy /dout high. on the 26th sclk, keep it high for as long as shutdown is desired. once sclk is pulled back low, the device automatically performs a self-calibration and, when the data is ready, the rdy /dout output goes low. see figure 5. this also achieves the purpose of single conversions with self- calibration. maxim integrated 24-bit, single-channel, ultra-low-power, delta sigma adc with 2-wire serial interface max11202
11 figure 1. timing diagram for data read after conversion figure 2. timing diagram for data read followed by rdy /dout being asserted high using 25th sclk figure 3. timing diagram for data read followed by two extra clock cycles for self-calibration t 5 t 3 1 d23 conversion is done data is available conversion is done data is available d22 d0 23 24 t 1 t 4 t 7 t 2 t 6 sclk rdy/dout 1 d23 conversion is done data is available conversion is done data is available d22 d0 23 24 25 sclk rdy/dout 25th slk rising edge pulls rdy/dout high 1 d23 conversion is done data is available conversion is done data is available after calibratio n calibration starts on 26th sclk t 8 d22 d0 23 24 12 25 26 d23 d22 sclk rdy/dout 25th sclk pulls rdy/dout high maxim integrated 24-bit, single-channel, ultra-low-power, delta sigma adc with 2-wire serial interface max11202
12 figure 5. timing diagram for sleep mode activation followed by self-calibration at wake-up figure 4. timing diagram for data read followed by sleep mode activation; single conversion timing sleep mode 12 12 3 24 25 26 conversion is done data is available t 12 t 10 device enters sleep mode device exits out sleep mode and starts calibration d0 rdy/dout d23 d22 d23 d22 sclk conversion is done data is available after calibration 25th sclk pulls rdy/dout high sleep mode 12 12 3 24 conversion is done data is available t 9 t 11 t 10 device enters sleep mode device exits out sleep mode d0 rdy/dout d23 d22 d23 d22 sclk conversion is done data is available maxim integrated 24-bit, single-channel, ultra-low-power, delta sigma adc with 2-wire serial interface max11202
13 applications information see figure 6 for the rtd temperature measurement circuit and figure 7 for a resistive bridge measurement circuit. figure 6. rtd temperature measurement circuit figure 7. resistive bridge measurement circuit package information for the latest package outline information and land patterns, go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a dif - ferent suffix character, but the drawing pertains to the package regardless of rohs status. package type package code document no. 10 max u10+2 21-0061 chip information process: bicmos i ref2 i ref1 i ref1 = k x i ref2 refp refn r ref ainp ainn gnd r rtd max11202 refp avdd refn ainp ainn max11202 maxim integrated 24-bit, single-channel, ultra-low-power, delta sigma adc with 2-wire serial interface max11202
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. 14 maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ? 2010 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/10 initial release 24-bit, single-channel, ultra-low-power, delta sigma adc with 2-wire serial interface max11202

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